Avionics is the nerve of modern fighters. The heart of avionics is an airborne computer. The distributed computer system for the avionics used for fourth generation fighters (DCS) is researched in the dissertation. The research's aim is to develop a suit of airborne computer system for fourth generation fighter's avionics application, as hard basis for further development of fourth generation fighter's avionics.
Based on analyzing the requirements of avionics for fourth generation fighters, according to China's situation, the distributed architecture is proposed in this dissertation. The distributed architecture consists of a number of clusters connected by fiber network (FDDI) . Each cluster consists of a number of sub-clusters which share a global bulk memory. In each sub-cluster, a number of modules are connected by data transfer bus (PI-BUS) and test & maintenance bus (TM-BUS) . The architecture has better merits as compared with foreign counterparts, including scalability, suitability and ease to realize.
The second problem we studied in this dissertation is the design and implementation of PI-BUS controller. After comprehensively analyzing PI-BUS protocol and INTEL products, according to PI-BUS'S data transmission principle, the PI-BUS controller architecture is proposed. Using programmable VLSI chips (FPGA) and VHDL language, we designed and implemented the PI-BUS controller with our own intellectual property. The PI-BUS controller is compatible with INTEL products at software level, which successfully broke the foreign technical blockade.
The third problem we studied in this dissertation is the design and implementation of system test. After comprehensively analyzing the characteristics of typical test methods, the test architecture and test method of DCS are presented. According to real level of test technology, TM-BUS implementation scheme is presented. A TM-BUS master control management technique with floating characteristic and the related controller architecture are also presented to support high reliable applications. Using programmable VLSI chips (FPGA) and VHDL language, we designed and implemented the TM-BUS controller with our own intellectual property.
The fourth problem we studied in this dissertation is the architecture and implementation of global bulk memory. After comprehensively analyzing the requirements of avionics'information sharing and avionics'characteristics, we developed a global bulk memory (GBM) architecture, consisting of memory modules, which is based on only one kind of memory module. The GBM has merits of good scalability, high transmission speed, less lines, simple structure and fault-tolerance. The GBM not only meets the requirements of the avionics used for fourth generation fighters, but also can be applied to massive parallel processing (MPP) systems with similar architecture.
The fifth problem we studied in this dissertation is the fault-tolerant technique of DCS. After analyzing various factors which affect the effectiveness of reconfiguration, we developed the method to locate faults, with the help of combination of hardware, software and TM-BUS. Based on these works, the system reconfiguration algorithm and reconfiguration mode are proposed. Compared with other related work, the fault-tolerant method not only developed the effectiveness of reconfiguration, but also reduced the performance decreasing speed.
The last problem we studied in this dissertation is the evaluation to the performance of DCS. Through communication delay analysis, we showed the method to decrease communication delay. The system real-time parameters were measured and analyzed. After analyzing two kinds of fault modes in system reliability evaluation, we realized qualitative evaluation to the reliability of DCS.