面向第四代战斗机航空电子系统应用的分布式计算机系统研究与实现

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摘要:

航空电子系统是现代飞行器的神经系统,机载计算机是现代航空电子系统的“心脏”。本文主要研究面向第四代战斗机航空电子系统应用的分布式计算机系统,目标是研制一套能够满足这种应用要求的分布式计算机系统,为第四代战斗机航空电子系统研制打下坚实基础。

本文在分析了第四代战斗机航空电子系统的需求的基础上,借鉴国外机载计算机的成功经验,结合我国国情,提出了一种分布式计算机体系结构。该分布式结构是通过光纤网络(FDDI)连接多个机群(cluster),机群是由多个子机群通过共享全局存储器组成,而子机群是采用具有消息传递机制的数据通信总线 (PI-BUS)及测试维护总线(TM-BUS)互连的多机系统。与国外同类结构相比,具有更好的可扩展性、更好的适应性及易实现等特点。

本文研究的第二个问题是PI-BUS控制器设计与实现。经过对PI-BUS协议及INTEL公司产品的分析,根据PI-BUS数据传输原理,提出了PI-BUS控制器结构。运用可编程VLSI芯片(FPGA)及VHDL硬件描述语言,完成了具有自主知识产权的PI-BUS控制器设计与实现,达到在软件级与INTEL公司产品完全兼容,彻底打破了国外对该关键技术的封锁。

本文研究的第三个问题是系统测试技术研究与实现。综合分析了典型测试方法的优缺点,提出了面向第四代战斗机航空电子系统应用的分布式计算机系统测试体系结构与测试方法。根据测试技术发展的实际水平,提出了TM-BUS实现方案。为满足高可靠应用的要求,提出了TM-BUS MASTER的浮动控制管理机制及其控制器结构。运用可编程VLSI芯片(FPGA)及VHDL硬件描述语言,完成了具有自主知识产权的TM-BUS控制器设计与实现,打破了国外对该关键技术的封锁。

本文研究的第四个问题是全局存储器体系结构与实现。分析了航空电子系统信息共享的需求,结合航空电子系统应用特点,提出了仅以一种存储器模块为基础,通过互连多个存储器模块构成的全局存储器的体系结构,完成了该全局存储器的设计与实现。该全局存储器具有可扩充性好、传输速率高、连线少、结构简单及容错等特点。不仅可满足第四代战斗机航空电子系统应用的要求,而且可用于其它类似结构的大规模并行处理系统中。

本文研究的第五个问题是面向第四代战斗机航空电子系统应用的分布式计算机系统容错技术。分析了影响重构有效性的各因素,提出了在TM-BUS的辅助下,采用软硬件相结合的方法实现故障的快速检测与定位算法。在此基础上,提出了系统重构模式及重构算法。与相关工作相比,提高了重构有效性,降低了系统降级速度。

本文研究的最后一个问题是对面向第四代战斗机航空电子系统应用的分布式计算机系统性能进行综合评价。系统分析了通信延迟,指出了减小通信延迟的方法。测试并分析了系统的实时性能。分析了系统可靠性建模中的两种失效模式,实现了对系统可靠性进行定性评估。



Abstract

Avionics is the nerve of modern fighters. The heart of avionics is an airborne computer. The distributed computer system for the avionics used for fourth generation fighters (DCS) is researched in the dissertation. The research's aim is to develop a suit of airborne computer system for fourth generation fighter's avionics application, as hard basis for further development of fourth generation fighter's avionics.

Based on analyzing the requirements of avionics for fourth generation fighters, according to China's situation, the distributed architecture is proposed in this dissertation. The distributed architecture consists of a number of clusters connected by fiber network (FDDI) . Each cluster consists of a number of sub-clusters which share a global bulk memory. In each sub-cluster, a number of modules are connected by data transfer bus (PI-BUS) and test & maintenance bus (TM-BUS) . The architecture has better merits as compared with foreign counterparts, including scalability, suitability and ease to realize.

The second problem we studied in this dissertation is the design and implementation of PI-BUS controller. After comprehensively analyzing PI-BUS protocol and INTEL products, according to PI-BUS'S data transmission principle, the PI-BUS controller architecture is proposed. Using programmable VLSI chips (FPGA) and VHDL language, we designed and implemented the PI-BUS controller with our own intellectual property. The PI-BUS controller is compatible with INTEL products at software level, which successfully broke the foreign technical blockade.

The third problem we studied in this dissertation is the design and implementation of system test. After comprehensively analyzing the characteristics of typical test methods, the test architecture and test method of DCS are presented. According to real level of test technology, TM-BUS implementation scheme is presented. A TM-BUS master control management technique with floating characteristic and the related controller architecture are also presented to support high reliable applications. Using programmable VLSI chips (FPGA) and VHDL language, we designed and implemented the TM-BUS controller with our own intellectual property.

The fourth problem we studied in this dissertation is the architecture and implementation of global bulk memory. After comprehensively analyzing the requirements of avionics'information sharing and avionics'characteristics, we developed a global bulk memory (GBM) architecture, consisting of memory modules, which is based on only one kind of memory module. The GBM has merits of good scalability, high transmission speed, less lines, simple structure and fault-tolerance. The GBM not only meets the requirements of the avionics used for fourth generation fighters, but also can be applied to massive parallel processing (MPP) systems with similar architecture.

The fifth problem we studied in this dissertation is the fault-tolerant technique of DCS. After analyzing various factors which affect the effectiveness of reconfiguration, we developed the method to locate faults, with the help of combination of hardware, software and TM-BUS. Based on these works, the system reconfiguration algorithm and reconfiguration mode are proposed. Compared with other related work, the fault-tolerant method not only developed the effectiveness of reconfiguration, but also reduced the performance decreasing speed.

The last problem we studied in this dissertation is the evaluation to the performance of DCS. Through communication delay analysis, we showed the method to decrease communication delay. The system real-time parameters were measured and analyzed. After analyzing two kinds of fault modes in system reliability evaluation, we realized qualitative evaluation to the reliability of DCS.


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本文内容于 2008-1-27 0:45:12 被zhao2365192编辑

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